View CY62167EV18LL-55BVI_4810026.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY62167EV18 MoBL(R)
16 Mbit (1M x 16) Static RAM
Features

Very high speed: 55 ns Wide voltage range: 1.65V to 2.25V Ultra low standby power Typical standby current: 1.5 A Maximum standby current: 12 A Ultra low active power Typical active current: 2.2 mA at f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb-free 48-ball VFBGA packages
by 99 percent when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: the device is deselected (CE1HIGH or CE2 LOW); outputs are disabled (OE HIGH); both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH); and a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Functional Description
The CY62167EV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
1M x 16 RAM ARRAY
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
CE2
BHE
Power Down Circuit
A11 A12 A13 A14 A15 A16 A17 A18 A19
CE1 BHE BLE
WE OE BLE
CE2 CE1
Cypress Semiconductor Corporation Document #: 38-05447 Rev. *G
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 13, 2009
[+] Feedback
CY62167EV18 MoBL(R)
Pin Configuration
Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View [1, 2, 3]
1 BLE IO 8 IO 9 VSS VCC IO 14 IO 15 A18 2 OE BHE IO 10 IO11 IO 12 IO 13 A19 A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 IO 1 IO3 IO 4 IO 5 WE A11 6 CE2 IO 0 IO 2 Vcc Vss IO 6 IO 7
NC
A B C D E F G H
Product Portfolio
Power Dissipation Product VCC Range (V) Min CY62167EV18LL CY62167EV30LL[5] 1.65 Typ[4] 1.8 Max 2.25 55 Speed (ns) Typ[4] 2.2 Operating ICC (mA) f = 1 MHz Max 4.0 f = fmax Typ[4] 25 Max 30 Standby ISB2 (A) Typ[4] 1.5 Max 12
Notes 1. The information related to 6 x 7 x 1 mm VFBGA package is preliminary. 2. NC pins are not connected on the die. 3. Ball H6 for the VFBGA package can be used to upgrade to a 32M density. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 5. This part can be operated in the VCC range of 1.65V-2.25V at 55ns speed. It can also be operated in the VCC range of 2.2V-3.6V at 45ns speed.
Document #: 38-05447 Rev. *G
Page 2 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied ........................................... -55C to + 125C Supply Voltage to Ground Potential .......................... -0.2V to 2.45V (VCC(max) + 0.2V) DC Voltage Applied to Outputs in High Z State[6, 7]........... -0.2V to 2.45V (VCC(max) + 0.2V) DC Input Voltage[6, 7] ....... -0.2V to 2.45V (VCC(max) + 0.2V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA
Operating Range
Device CY62167EV18LL Range Ambient Temperature VCC[8] Industrial -40C to +85C 1.65V to 2.25V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power Down Current - CMOS Inputs Test Conditions IOH = -0.1 mA IOL = 0.1 mA VCC = 1.65V to 2.25V VCC = 1.65V to 2.25V GND < VI < VCC GND < VO < VCC, Output Disabled f = fmax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels 1.4 -0.2 -1 -1 25 2.2 1.5 55 ns Min 1.4 0.2 VCC + 0.2V 0.4 +1 +1 30 4.0 12 Typ[4] Max Unit V V V V A A mA mA A
ISB1
CE1 > VCC - 0.2V or CE2 < 0.2V VIN > VCC - 0.2V, VIN < 0.2V) f = fmax(Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = VCC(max) CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = VCC(max)
ISB2[9]
Automatic CE Power Down Current - CMOS Inputs
1.5
12
A
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 6. VIL(min) = -2.0V for pulse durations less than 20 ns. 7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 8. Full Device AC operation is based on a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 9. Only chip enables (CE1 and CE2), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 38-05447 Rev. *G
Page 3 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Figure 2. AC Test Loads and Waveforms VCC OUTPUT R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board VFBGA VFBGA (6 x 7 x 1mm) (6 x 8 x 1mm) 27.74 9.84 55 16 Unit C/W C/W
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters R1 R2 RTH VTH 1.8V 13500 10800 6000 0.80 Unit V
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR[9] tCDR[10] tR[11] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Figure 3. Data Retention Waveform VCC(min) tCDR DATA RETENTION MODE VDR > 1.0 V VCC(min) tR VCC = 1.0V, CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min 1.0 10 Typ[4] Max Unit V A ns ns
VCC
CE1 or BHE.BLE
[12]
or
CE2
Notes 10. Tested initially and after any design or process changes that may affect these parameters. 11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 12. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05447 Rev. *G
Page 4 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Switching Characteristics
Over the Operating Range[13, 14] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[17]
Description
55 ns Min 55 55 10 55 25 5 18 10 18 0 55 55 10 18 55 40 40 0 0 40 40 25 0 20 10 Max
Unit
Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to OE HIGH to Low-Z[15] High-Z[15, 16] High-Z[15, 16]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW and CE2 HIGH to Low-Z[15] CE1 HIGH and CE2 LOW to CE1 LOW and CE2 HIGH to Power Up CE1 HIGH and CE2 LOW to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to BLE/BHE HIGH to Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z WE HIGH to
[15, 16]
Low-Z[15] High-Z[15, 16]
Low-Z[15]
Notes 13. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 1V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4. 14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state. 17. The internal memory write time is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05447 Rev. *G
Page 5 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Switching Waveforms
Figure 4 shows address transition controlled read cycle waveforms.[18, 19] Figure 4. Read Cycle No. 1
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 5 shows OE controlled read cycle waveforms.[19, 20] Figure 5. Read Cycle No. 2
ADDRESS tRC CE1 CE2 tACE BHE/BLE tDBE tLZBE OE tDOE DATA VALID tHZOE HIGH IMPEDANCE tHZBE tPD tHZCE
DATA OUT
tLZOE HIGH IMPEDANCE tLZCE
VCC SUPPLY CURRENT
tPU
50%
50%
ICC ISB
Notes 18. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 19. WE is HIGH for read cycle. 20. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05447 Rev. *G
Page 6 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Switching Waveforms (continued)
Figure 6 shows WE controlled write cycle waveforms.[17, 21, 22] Figure 6. Write Cycle No. 1
tWC ADDRESS tSCE CE1 CE2 tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 23 tHZOE VALID DATA
tHD
Notes 21. Data IO is high impedance if OE = VIH. 22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 23. During this period the IOs are in output state. Do not apply input signals.
Document #: 38-05447 Rev. *G
Page 7 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Switching Waveforms (continued)
Figure 7 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22] Figure 7. Write Cycle No. 2
tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA
WE
BHE/BLE
tBW
OE DATA I/O NOTE 23 tHZOE
tSD VALID DATA
tHD
Figure 8 shows WE controlled, OE LOW write cycle waveforms.[22] Figure 8. Write Cycle No. 3
tWC ADDRESS tSCE CE1 CE2
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATA I/O NOTE 23 VALID DATA
tHD
tHZWE
tLZWE
Document #: 38-05447 Rev. *G
Page 8 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Switching Waveforms (continued)
Figure 9 shows BHE/BLE controlled, OE LOW write cycle waveforms.[22] Figure 9. Write Cycle No. 4
tWC ADDRESS
CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA IO NOTE 23 VALID DATA tHD tBW tHA
Truth Table
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE BLE X X H L H L L H L L H L X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0-I/O15) Data Out (I/O0-I/O7); High Z (I/O8-I/O15) High Z (I/O0-I/O7); Data Out (I/O8-I/O15) High Z High Z High Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); High Z (I/O8-I/O15) High Z (I/O0-I/O7); Data In (I/O8-I/O15) Mode Deselect / Power Down Deselect / Power Down Deselect / Power Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Document #: 38-05447 Rev. *G
Page 9 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Ordering Information
Speed (ns) 55 Ordering Code CY62167EV18LL-55BAXI CY62167EV18LL-55BVI CY62167EV18LL-55BVXI CY62167EV30LL-45BVI
[5]
Package Diagram 51-85150 51-85150
Package Type 48-ball VFBGA (6 x 8 x 1 mm) 48-ball VFBGA (6 x 8 x 1 mm) (Pb-free) 48-ball VFBGA (6 x 8 x 1 mm)
Operating Range Industrial
001-13297 48-ball VFBGA (6 x 7 x 1 mm) (Pb-free)
Package Diagram
Figure 10. 48-Ball VFBGA (6 x 7 x 1 mm), 001-13297
NOTES: 1. ALL DIMENSION ARE IN MM [MAX/MIN] 2. JEDEC REFERENCE : MO-216 3. PACKAGE WEIGHT : 0.03g
001-13297-*A
Document #: 38-05447 Rev. *G
Page 10 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Package Diagram
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C 1.00 MAX
SEATING PLANE 0.26 MAX. C
51-85150-*D
Document #: 38-05447 Rev. *G
Page 11 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Document History Page
Document Title: CY62167EV18 MoBL(R) 16 Mbit (1M x 16) Static RAM Document Number: 38-05447 REV. ** *A ECN NO. 202600 463674 Orig. of Change AJU NXR Submission date 01/23/2004 See ECN Description of Change New Data Sheet Converted from Advance Information to Preliminary Changed VCC(max) from 2.20V to 2.25V Removed `L' bin and 35 ns speed bin from product offering Changed ball E3 from DNU to NC Removed redundant foot note on DNU Changed the ISB2(typ) value from 1.3 A to 1.5 A Changed the ICC(max) value from 40 mA to 25 mA Changed the AC Test Load Capacitance value from 50 pF to 30 pF Corrected typo in Data Retention Characteristics (tR) from 100 s to tRC ns Changed the ICCDR Value from 8 A to 5 A Changed tOHA, tLZCE, tLZBE, and tLZWE from 6 ns to 10 ns Changed tLZOE from 3 ns to 5 ns Changed tHZOE, tHZCE, tHZBE, and tHZWE from 15 ns to 18 ns Changed tSCE, tAW, and tBW from 40 ns to 35 ns Changed tPE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Updated 48 ball FBGA Package Information Updated the Ordering Information table Minor Change: Moved to external web Replaced 45 ns speed bin with 55 ns speed bin Converted from preliminary to final Added footnote# 8 related ISB2 and ICCDR Changed ISB1 and ISB2 spec from 10 A to 12 A Changed ICCDR spec from 8 A to 10 A Added footnote# 13 related AC timing parameters Changed tWC spec from 45 ns to 55 ns Changed tSCE, tAW, tPWE, tBW spec from 35 ns to 40 ns Changed tHZWE spec from 18 ns to 20 ns Added 48-Ball VFBGA (6 x 7 x 1mm) package Added footnote# 1 related to FBGA package Updated Ordering Information table Added CY62167EV30LL-45BVI part in the Ordering Information table Added footnote# 5 related to CY62167EV30LL-45BVI part Added CY62167EV18LL-55BVI part in the Ordering Information table
*B *C *D
469182 619122 1130323
NSI NXR VKN
See ECN See ECN See ECN
*E
1388287
VKN
See ECN
*F *G
1664843 2675375
VKN/AESA VKN/PYRS
See ECN 03/17/2009
Document #: 38-05447 Rev. *G
Page 12 of 13
[+] Feedback
CY62167EV18 MoBL(R)
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
Products
PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
PSoC Solutions
General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
(c) Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05447 Rev. *G
Revised March 13, 2009
Page 13 of 13
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY62167EV18LL-55BVI

	To Download CY62167EV18LL-55BVI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .